Recently, with the widespread use of VLSI (very large scale integration), power control integrated circuits are generally provided with power devices, VLSI logic circuits, memory devices, CPUs (central processing units), etc., which are all fabricated on a single chip. To handle high voltages and currents, DMOS (double-diffused metal oxide semiconductor) transistors are conventionally used for the power devices, which can operate with low on-resistance while attaining high withstand voltage.
LDMOS transistors particularly have a simple structure suitable for incorporation into the VLSI logic circuits, however, they have been considered inferior to VDMOS (vertical double-diffused metal oxide semiconductor) transistors as they have high on-resistance. Recently, RESURF (reduced surface field) LDMOS transistors, capable of providing low on-resistance, are introduced and are increasingly used in the power devices.
FIG. 1 illustrates a section of a background LDMOS transistor, including a substrate 101, a well region 109, a first oxide region 111, a second oxide region 113, a gate oxide region 115, a gate electrode 117, a channel well region 119, a source region 121, and a drain region 123.
The background LDMOS transistor of FIG. 1 is manufactured as follows. First, the well region 109 is diffused in the substrate 101. The oxide regions 111, 113 are formed on the respective surfaces of the well region 109. The gate oxide region 115 is formed over the substrate 101, except for the portion having the oxide layers 111, 113. The gate electrode 117 is formed in between a portion of the well region 109 reserved for the source region 121 and a portion of the well region 109 reserved for the drain region 123, partially covering the portion reserved for the source region 121, and over the gate oxide region 115 and the second oxide region 113. The channel well region 119 is diffused in the well region 109, by implanting and thermally diffusing impurity ions, using one side edge (towards the portion for forming the source region 121) of the gate electrode 117 as a mask. The source region 121 is diffused in the channel well region 119, by implanting and thermally diffusing impurity ions, in the self-aligned manner with respect to the gate electrode 117. The drain region 123 is additionally diffused in the well region 109, between the first and second oxide regions 111, 113 apart from the gate electrode 117, in the self-aligned manner with respect to the second oxide region 113.
One problem of the background LDMOS transistor of FIG. 1 is that the second oxide region 113 interrupts a current flowing from the source region 121 to the drain region 123. This eventually increases on-resistance of the background LDMOS transistor.
To solve this problem, the first and second oxide regions 111, 113 may be eliminated, as illustrated in FIG. 2.
In this case, a resist pattern 125 is additionally provided at the other side edge (towards the drain region 123) of the gate electrode 117 so as to cover a surface of the well region 109 via the gate oxide region 115.
To fabricate the semiconductor device of FIG. 2, the well region 109 is firstly formed in the substrate 101. After depositing the gate oxide region 115, the gate electrode 117 is formed thereon, apart from the drain region 123. The channel well region 119 is diffused in the self-aligned manner with respect to the gate electrode 117. The resist pattern 125 is then formed, and the source region 121 is diffused in the channel well region 119, using the resist pattern 125 as a mask, by implanting impurities, in the self-aligned manner with respect to the gate electrode 117. Subsequently, the drain region 123 is diffused in the well region 109, apart from the gate electrode 117. After formation of the source and drain regions 121 and 123, the resist pattern 125 is removed.
However, the above-described manufacturing method easily causes misalignment of the drain region 123, which is desirably formed apart from the gate electrode 117 for high withstand voltage. To prevent such misalignment, the background LDMOS transistor of FIG. 2 generally has a larger cell size, and suffers from high on-resistance variation. Further, the side edge portion of the gate electrode 117, which is covered by the resist pattern 125, is not implanted with the impurities. That is, a right portion of the gate electrode 117 (See FIG. 2) remains as non-doped and it easily causes the popping phenomenon.
To prevent this popping phenomenon, the gate electrode 117 may be doped before forming the channel well region 119. However, this may cause low withstand voltage.
FIG. 3 illustrates a section of another background LDMOS transistor, when manufactured together with another MOS transistor, particularly, a CMOS (complementary metal oxide semiconductor). During formation of the gate electrode 117, an oxide side wall 127 is usually formed at each side portion of the gate electrode 117. This sometimes causes the source region 121 to form at a position apart from the side portion of the gate electrode 127. Therefore, the source region 121 becomes as an offset region, and causes the LDMOS transistor to be inoperative.
To prevent this problem, a background LDMOS transistor of FIG. 4 further includes a diffused layer 129 of LDD (lightly doped drain) structure, which has a lower impurity concentration than that of the source region 121. However, addition of the diffused layer 129 may increase resistance of the source region 121, thereby increasing on-resistance of the background LDMOS transistor.
Any one of the above-described or other background LDMOS transistors has another problem, when manufactured with other MOS transistors. To attain a high withstand voltage, the channel well region 119 is usually formed with high temperature of about 1100 degrees C. Under such a high temperature, the other MOS transistors may suffer from redistribution of impurity ions that have been implanted in the channel well regions. This may cause the withstand voltage of the other MOS transistors to decrease.